Abstracts of MSc Theses: 2002


List of MSc Theses: 2002

  1. Adam Rhett Isaacson A 500kHz to 5MHz Stepped Frequency Borehole Tomographic Imaging System.
  2. Clifford Leonard van Dyk The Design and Implementation of a Wideband Digital Radio Receiver.
  3. Carl Frans van Schaik The Development of a Node for a Hardware Reconfigurable Parallel Processor.

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Isaacson A R

A 500kHz to 5MHz Stepped Frequency Borehole Tomographic Imaging System


The aim of this thesis is the design integration and testing of a bistatic stepped frequency radar covering the band 500kHz to 5 MHz. Some results are given from the simulation of tomography exploiting phase information that would be available from such a system.

Professor Iain Mason, of the University of Sydney, De Beers, and Reutech Radar Systems sponsored the Radar Remote Sensing Group at UCT to develop a prototype, CW Stepped Frequency Borehole Tomographic Imaging System, proposed by Dr Alan Langman of the University of Cape Town. The system is to demonstrate that a coherent system can be achieved using DDS technology.

This dissertation involves a study of Cross-Borehole Tomography. The mathematical physical models of the Radon Transform are reviewed. The entire Cross-Borehole Tomographic process is simulated, based on these physical models of the Radon Transform. The system specifications for the final design are based on the results from the simulation. Finally, the final design is built, and tested.

The phase yields a better quality of image reconstruction when compared to amplitude, and hence a coherent system is a good choice. The system is frequency to frequency coherent for the entire transmit frequency range, which satisfies the main aim of this dissertation.

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Van Dyk C L

The Design and Implementation of a Wideband Digital Radio Receiver


Historically radio has been implemented using largely analogue circuitry. Improvements in mixed signal and digital signal processing technology are rapidly leading towards a largely digital approach, with down-conversion and filtering moving to the digital signal processing domain. Advantages of this technology include increased performance and functionality, as well as reduced cost.

Wideband receivers place the heaviest demands on both mixed signal and digital signal processing technology, requiring high spurious free dynamic range (SFDR) and signal processing bandwidths. This dissertation investigates the extent to which current digital technology is able to meet these demands and compete with the proven architectures of analogue receivers. A scalable generalised digital radio receiver capable of operating in the HF and VHF bands was designed, implemented and tested, yielding instantaneous bandwidths in excess of 10 MHz with a spurious-free dynamic range exceeding 80 decibels below carrier (dBc).

The results achieved reflect favourably on the digital receiver architecture. While the necessity for minimal analogue circuitry will possibly always exist, digital radio architectures are currently able to compete with analogue counterparts. The digital receiver is simple to manufacture, based on the use of largely commercial off-the-shelf (COTS) components, and exhibits extreme flexibility and high performance when compared with comparably priced analogue receivers.

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Van Schaik C F

The Development of a Node for a Hardware Reconfigurable Parallel Processor


This dissertation concerns the design and implementation of a node for a hardware reconfigurable parallel processor. The hardware that was developed allows for the further development of a parallel processor with configurable hardware acceleration. Each node in the system has a standard microprocessor and reconfigurable logic device and has high speed communications channels for inter-node communication.

The design of the node provided high speed serial communications channels allowing the implementation of various network topographies. The node also provided a PCI master interface to provide an external interface and communicate with local nodes on the bus. A high speed RISC processor provided communications and system control functions and the reconfigurable logic device provided communication interfaces and data processing functions.

The node was designed and implemented as a PCI card that interfaced a standard PCI bus. VHDL designs for logic devices that provided system support were developed, VHDL designs for the reconfigurable logic FPGA and software including drivers and system software were written for the node. The 64-bit version Linux operating system was then ported to the processor providing a UNIX environment for the system.

The node functioned as specified and parallel and hardware accelerated processing was demonstrated. The hardware acceleration was shown to provide substantial performance benefits for the system.

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